Conventional nonvolatile memory devices include mask read-only memories (ROMs), electrically erasable programmable read-only memories (EEPROMs), and flash EEPROMs. These conventional nonvolatile memory devices typically include memory cells that can store one of two information states, e.g., an "ON" state and an "OFF" state, In order to store N-bits of data, N single-bit memory cells are typically used.
Many conventional transistor-type one-bit memory cells define logical states using the threshold voltage of a transistor, i.e., the state of data stored in a transistor may be distinguished by the level of the threshold voltage of the transistor. In a typical mask ROM, threshold voltage for a cell transistor is controlled by injection of ions using ion implantation techniques. In typical EPROMs, EEPROMs and flash EEPROMs, threshold voltage for a cell transistor is controlled by controlling the amount of charge stored in a floating gate of the transistor.
Threshold voltage control can be used to implement a transistor memory cell that is capable of representing multiple bits of information. For example, as illustrated in FIG. 1, cell transistors of a mask ROM may be programmed with logical values "00", "01", "10" or "11", by setting their threshold levels at a value falling within one of four ranges around nominal threshold voltages Vth1, Vth2, Vth3, Vth4.
FIG. 2 is a diagram showing a voltage variation applied to a word line during a data reading operation for a conventional multi-level memory device such as the mask ROM device 1 of FIG. 3. Referring to FIG. 3, the multilevel mask ROM memory device 1 comprises a memory cell array 10 including a plurality of nonvolatile memory cells respectively arranged at intersections of word lines and bit lines (not shown). Each of the nonvolatile memory cells is operative to store multi-bit data, i.e., can support a plurality of threshold voltages. For example, to store two bits, each nonvolatile memory cell may take on one of the four threshold voltages Vth1, Vth2, Vth3,Vth4 illustrated in FIG. 1. One of the word lines is selected by a row decoder circuit 20, and at least one bit line is selected by a column decoder circuit 40. The selected word line is sequentially driven at different word line voltages V.sub.WLi (e.g., i=1, 2, 3) supplied by a word line voltage generating circuit 30. The word line voltage generating circuit 30 sequentially generates the different word line voltages V.sub.WLi in response to sensing period signals STGi from a sensing period signal generating circuit 50. As illustrated in FIG. 2, the word line voltages may be varied from lower levels to higher levels during a read cycle, but those skilled in the art will appreciate that the voltages may be varied in other way, e.g., from higher levels to lower levels. An example of a word line voltage generating circuit is described in U.S. Pat. No. 5,457,650 to Sugiura et al.
The sensing period signal generating circuit 50 generates sensing period signals STGi and a sensing enable signal SAen. The signals STGi define sensing periods t1, t2, t3, respectively, and the sensing enable signal SAen is a pulse asserted at predetermined sensing points within the sensing periods. Data stored in a nonvolatile memory cell selected by the row and column decoder circuits 20, 40 is sensed, amplified, and latched by a sense amplifier and data latch circuit 60 that is responsive to the sensing period signals STGi and the sensing enable signal SAen. The data latched in the sense amplifier and data latch circuit 60 is output via a data output circuit 70.
FIG. 4 illustrates a sensing period signal generating circuit 50 according to the prior art. The circuit 50 includes a ring oscillator 51, a plurality of serially connected counters 52-54, first, second and third sensing period signal generators 55, 56, 57, and a sensing enable signal generator 58. The ring oscillator 51 generates a clock signal CLK in response to an oscillator enable signal OSCen. The counters 52-54 produce clock signals Pi (i=1, 2, . . . , n), wherein the clock signal produced by a respective one of the counters 52-54 has a period twice that of the clock signal input thereto. The counters 52-54 are reset (initialized) by a reset signal RST. The first, second and third sensing period signal generators 55, 56, 57 generate first, second and third sensing period signals STG1, STG2, STG3, respectively, in response to the clock signals P1-Pm from the counters 52-54, synchronized with the clock signal CLK. The sensing periods t1, t2, t3 defined by the sensing period signals STG1, STG2, STG3 typically have the same duration. The sensing enable signal generator 58 also generates the sensing enable signal SAen responsive to the clock signals P1-Pm.
FIG. 5 is a timing diagram illustrating a conventional data reading operation for a multi-level memory device such as the nonvolatile semiconductor memory device 1 of FIG. 3. Before reading a two-bit cell, the reset signal RST is taken to a "high" level, resetting the counters 52-54 in the sensing period signal generating circuit 50. A memory cell is selected by the row and column decoder circuits 20, 40 according to row and column address signals, and a word line connected to the selected (addressed) memory cell is driven with a first word line voltage V.sub.WL1 from the word line voltage generating circuit 30 during a first sensing period t1. A sense amplifier in the sensing amplifier and data latch circuit 60 detects whether a current flows through the selected memory cell when the sensing enable signal SAen is asserted, and data on a data line DL.sub.j is sensed and latched in the circuit 60. If the applied word line voltage turns the selected memory cell "ON", the output on the data line DL.sub.j takes on a "high" level. If the cell remains "OFF", the output on the data line DL.sub.j takes on a "low" level.
A second word line voltage V.sub.WL2 higher than the first word line voltage V.sub.WL1 is next applied to the selected word line during a second sensing period t2. A sense amplifier detects whether current flows through the selected memory cell when the sensing enable signal SAen is asserted. As in the first sensing period t1, data thus sensed is temporarily stored in the circuit 60. Similarly, a third word line voltage V.sub.WL3 higher than the first and second word line voltages V.sub.WL1, V.sub.WL2 is applied to the word line during a third sensing period t3, and a sense amplifier detects whether current flows through the selected memory cell when the sensing enable signal SAen is asserted. Data thus sensed is latched in the circuit 60.
The above-described conventional multi-level memory device may have potential disadvantages. If the gate-source voltage V.sub.gs applied to the selected memory cell in each of the sensing periods t1, t2, t3 is the same, the cell currents Icell00, Icell01, Icell10 generated for cells programmed at different logic states "00", "01" and "10" differ, as shown in FIG. 6. Consequently, the times needed for sufficient charge transfer to sense the respective data states of the differently programmed cells may differ. At one extreme, using a sensing time based on the "00" state may provide insufficient time for charge transfer to sense the "01" and "10" states, potentially leading to data sensing errors. At another extreme, however, use of a sensing time based on the "10" state may increase data access time and current consumption, leading to reduced reliability and shortened battery lifetime in low-power applications.